200 Mbps-optical integrated circuit design and first iteration realizations in 1.2 and 0.8 micron Bi-CMOS technology

L. W. Snyman, C. T. Chaing, A. Bogalecki, M. Du Plessis, H. Aharoni

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

A prototype Silicon CMOS Optical Integrated Circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 micron Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS trans-impedance analogue amplifiers. Simulations with MicroSim PSpice software predict a utilizable bandwidth capability of up to 220 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 n A to 100 n A and driving a 10mV to 1 V signal into a 100 kΩ load. First iteration OEIC structures were realised in 1.2 micron CMOS technology for various source-waveguide-detector arrangements. Current signal ranging from InA to 1 micro-amp was detected at detectors. The technology seems favorable for first-iteration implementation for digital communications on chip up to 200Mbps.

Original languageEnglish
Pages (from-to)25-34
Number of pages10
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume5357
DOIs
StatePublished - 13 Sep 2004
Externally publishedYes
EventOptoelectronic Integration on Silicon - San Jose, CA, United States
Duration: 27 Jan 200428 Jan 2004

Keywords

  • CMOS technology
  • Opto-electronic integrated circuits
  • Silicon LED's

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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