200 Mbps-optical integrated circuit design and first iteration realizations in 1.2 and 0.8 micron Bi-CMOS technology

A prototype Silicon CMOS Optical Integrated Circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 micron Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS trans-impedance analogue amplifiers. Simulations with MicroSim PSpice software predict a utilizable bandwidth capability of up to 220 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 n A to 100 n A and driving a 10mV to 1 V signal into a 100 kΩ load. First iteration OEIC structures were realised in 1.2 micron CMOS technology for various source-waveguide-detector arrangements. Current signal ranging from InA to 1 micro-amp was detected at detectors. The technology seems favorable for first-iteration implementation for digital communications on chip up to 200Mbps.