A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications

Amit Kazimirsky, Adam Teman, Noa Edri, Alexander Fish

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The diminishing returns provided by voltage scaling have led to a recent paradigm shift toward so-called 'approximate computing,' where computation accuracy is traded off for cost in error-tolerant applications. In this paper, a novel approach to achieving the power-performance-area versus data integrity tradeoff is proposed by integrating robust static memory cells and error-prone dynamic cells within a single array. In addition, the resulting integrated dynamic and static random access memory (iD-SRAM) provides the ability to trade off power consumption and accuracy on-the-fly according to the current conditions and operating mode. A 4-kB iD-SRAM array was implemented in a low-power, 65-nm CMOS technology, providing as much as an 80% power reduction and a 20% area reduction as compared with standard approaches, when applied to a video decoder at 500 MHz.

Original languageEnglish
Article number7956276
Pages (from-to)2411-2418
Number of pages8
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number9
DOIs
StatePublished - 1 Sep 2017
Externally publishedYes

Keywords

  • Approximate computing
  • DRAM
  • PPA tradeoff
  • SRAM
  • hybrid memory
  • integrated dynamic and static random access memory (iD-SRAM)
  • low power
  • video decoding

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