A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish

doi:10.1109/LSSC.2020.3011636

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Original language	English
Article number	9146537
Pages (from-to)	314-317
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	3
DOIs	https://doi.org/10.1109/LSSC.2020.3011636
State	Published - 1 Jan 2020
Externally published	Yes

Keywords

Adaptive design
digital signal processing (DSP)
dual-mode logic (DML)

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/LSSC.2020.3011636

Cite this

@article{2b5a4b2c146f41e69227309cfdc5bb67,

title = "A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET",

abstract = "The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.",

keywords = "Adaptive design, digital signal processing (DSP), dual-mode logic (DML)",

author = "Netanel Shavit and Inbal Stanger and Ramiro Taco and Marco Lanuzza and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2020",

month = jan,

day = "1",

doi = "10.1109/LSSC.2020.3011636",

language = "English",

volume = "3",

pages = "314--317",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers",

}

TY - JOUR

T1 - A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

AU - Shavit, Netanel

AU - Stanger, Inbal

AU - Taco, Ramiro

AU - Lanuzza, Marco

AU - Fish, Alexander

PY - 2020/1/1

Y1 - 2020/1/1

N2 - The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

AB - The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

KW - Adaptive design

KW - digital signal processing (DSP)

KW - dual-mode logic (DML)

UR - http://www.scopus.com/inward/record.url?scp=85089287793&partnerID=8YFLogxK

U2 - 10.1109/LSSC.2020.3011636

DO - 10.1109/LSSC.2020.3011636

M3 - Article

AN - SCOPUS:85089287793

SN - 2573-9603

VL - 3

SP - 314

EP - 317

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

M1 - 9146537

ER -

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Abstract

Keywords

ASJC Scopus subject areas

UN SDGs

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