A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Robert Giterman, Amir Shalom, Andreas Burg, Alexander Fish, Adam Teman

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations under technology scaling lead to a reduced data retention time (DRT), resulting in increased refresh power and reduced memory availability, currently limiting its implementation to planar 28-nm technologies and above. This letter presents the first gain-cell embedded DRAM (GC-eDRAM) in 16-nm FinFET technology, featuring a mixed- V_{T} 3T gain-cell structure to minimize the storage node (SN) leakage. The implemented 1-Mbit 3T GC-eDRAM is fully logic-compatible and provides a 2\times smaller bitcell size compared to a 6T SRAM with similar design rules, offering the highest density logic-compatible memory cell in 16-nm technology. Measurement results demonstrate a 77- \mu \text{s} DRT under a 600-mV V_{\text {DD}} , which is over 10\times longer than previously reported GC-eDRAMs in 28-nm technologies. The memory was fully operational at temperatures spanning -40 °C to 125 °C and under a supply voltage as low as 450 mV, providing the lowest measured V_{\text {DDmin}} and widest temperature range reported in the literature for GC-eDRAM.

Original languageEnglish
Article number9131838
Pages (from-to)110-113
Number of pages4
JournalIEEE Solid-State Circuits Letters
StatePublished - 1 Jan 2020
Externally publishedYes


  • Embedded DRAM
  • SRAM
  • gain cell (GC)
  • low voltage
  • retention time

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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