TY - GEN
T1 - A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI
AU - Giterman, Robert
AU - Teman, Adam
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].
AB - The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].
UR - http://www.scopus.com/inward/record.url?scp=85047758257&partnerID=8YFLogxK
U2 - 10.1109/S3S.2017.8308757
DO - 10.1109/S3S.2017.8308757
M3 - Conference contribution
AN - SCOPUS:85047758257
T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
SP - 1
EP - 3
BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
PB - Institute of Electrical and Electronics Engineers
T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Y2 - 16 October 2017 through 18 October 2017
ER -