A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI

Robert Giterman, Adam Teman, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].

Original languageEnglish
Title of host publication2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
PublisherInstitute of Electrical and Electronics Engineers
Pages1-3
Number of pages3
ISBN (Electronic)9781538637654
DOIs
StatePublished - 7 Mar 2018
Externally publishedYes
Event2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States
Duration: 16 Oct 201718 Oct 2017

Publication series

Name2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume2018-March

Conference

Conference2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/TerritoryUnited States
CityBurlingame
Period16/10/1718/10/17

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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