A 250 mV 8 kb 40 nm ultra-low power 9t supply feedback SRAM (SF-SRAM)

Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish

Research output: Contribution to journalArticlepeer-review

93 Scopus citations

Abstract

Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.

Original languageEnglish
Article number6008514
Pages (from-to)2713-2726
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number11
DOIs
StatePublished - 1 Nov 2011

Keywords

  • CMOS memory integrated circuits
  • SRAM
  • leakage suppression
  • ultra low power

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