TY - GEN
T1 - A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI
AU - Shalom, Amir
AU - Fish, Alexander
AU - Teman, Adam
N1 - Funding Information:
IV. ACKNOWLEDGMENTS This work was supported by the Israel Science Foundation (ISF) under grant number 996/2018.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10/14
Y1 - 2019/10/14
N2 - The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].
AB - The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].
UR - http://www.scopus.com/inward/record.url?scp=85100836101&partnerID=8YFLogxK
U2 - 10.1109/S3S46989.2019.9320704
DO - 10.1109/S3S46989.2019.9320704
M3 - Conference contribution
AN - SCOPUS:85100836101
T3 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
BT - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
PB - Institute of Electrical and Electronics Engineers
T2 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Y2 - 14 October 2019 through 17 October 2019
ER -