A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI

Amir Shalom; Alexander Fish; Adam Teman

doi:10.1109/S3S46989.2019.9320704

A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI

Amir Shalom, Alexander Fish, Adam Teman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].

Original language	English
Title of host publication	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Publisher	Institute of Electrical and Electronics Engineers
ISBN (Electronic)	9781728135236
DOIs	https://doi.org/10.1109/S3S46989.2019.9320704
State	Published - 14 Oct 2019
Externally published	Yes
Event	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, United States Duration: 14 Oct 2019 → 17 Oct 2019

Publication series

Name	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Conference

Conference	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Country/Territory	United States
City	San Jose
Period	14/10/19 → 17/10/19

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/S3S46989.2019.9320704

Cite this

Shalom, A., Fish, A., & Teman, A. (2019). A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 Article 9320704 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/S3S46989.2019.9320704

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title = "A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI",

abstract = "The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].",

author = "Amir Shalom and Alexander Fish and Adam Teman",

note = "Funding Information: IV. ACKNOWLEDGMENTS This work was supported by the Israel Science Foundation (ISF) under grant number 996/2018. Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 ; Conference date: 14-10-2019 Through 17-10-2019",

year = "2019",

month = oct,

day = "14",

doi = "10.1109/S3S46989.2019.9320704",

language = "English",

series = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019",

publisher = "Institute of Electrical and Electronics Engineers",

booktitle = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019",

address = "United States",

}

Shalom, A, Fish, A & Teman, A 2019, A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI. in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019., 9320704, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Institute of Electrical and Electronics Engineers, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, San Jose, United States, 14/10/19. https://doi.org/10.1109/S3S46989.2019.9320704

A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI. / Shalom, Amir; Fish, Alexander; Teman, Adam.
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers, 2019. 9320704 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Y1 - 2019/10/14

N2 - The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].

AB - The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].

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M3 - Conference contribution

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BT - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

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Shalom A, Fish A, Teman A. A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers. 2019. 9320704. (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). doi: 10.1109/S3S46989.2019.9320704

A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI

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