Abstract
A novel Dual Mode Square (DM2) adder is proposed. The DM2 adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the DM2 adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed DM2 approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD.
Original language | English |
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Article number | 6858090 |
Pages (from-to) | 3175-3183 |
Number of pages | 9 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 61 |
Issue number | 11 |
DOIs | |
State | Published - 1 Nov 2014 |
Externally published | Yes |
Keywords
- Adders
- DML
- low-power design
ASJC Scopus subject areas
- Electrical and Electronic Engineering