A low-power block-based CMOS image sensor with dual VDD

A novel low-power image sensor with dual analog power supply 1.8 and 1.1 V during image capture stage is proposed. Different from a traditional imager having a unique analog power for image capture, the proposed imager works on blocks of 8 × 8 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, high supply voltage will be chosen to achieve high imaging performance; otherwise, low supply voltage will be used to save power. In addition, the power gating method is applied to the additional computation circuits to save power further. Theoretical analysis and simulation results by Matlab and Cadence are given to demonstrate the efficiency of the proposed methodology. The amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB). The chip is implemented in TSMC 0.18 μm CMOS technology and simulated by Spectre Cadence. The total power consumption of the additional computation logic is only about 7.0 μW.