Abstract
Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32 × 32 bit memory macro was designed and fabricated in a standard 0.18-μm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.
Original language | English |
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Article number | 7404051 |
Pages (from-to) | 2622-2633 |
Number of pages | 12 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 24 |
Issue number | 8 |
DOIs | |
State | Published - 1 Aug 2016 |
Externally published | Yes |
Keywords
- Critical charge
- low voltage
- radiation effects
- radiation hardening
- single-event upset (SEU)
- soft errors
- space applications
- static random access memory (SRAM)
- subthreshold
- ultralow power (ULP)
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering