A minimum leakage quasi-static RAM bitcell

Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

Original languageEnglish
Pages (from-to)204-218
Number of pages15
JournalJournal of Low Power Electronics and Applications
Issue number1
StatePublished - 16 May 2011


  • CMOS memory integrated circuits
  • Dynamic noise margin
  • Leakage suppression
  • SRAM
  • Ultra low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A minimum leakage quasi-static RAM bitcell'. Together they form a unique fingerprint.

Cite this