A New Fast-Response Double-Loop Phase-Lock Loop

B. Z. Kaplan; M. Rolnick; D. Wulich

doi:10.1109/PROC.1986.13466

A New Fast-Response Double-Loop Phase-Lock Loop

B. Z. Kaplan
, M. Rolnick
, D. Wulich

Department of Electrical & Computer Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A new method of constructing phase-lock loop systems with wide capture range and fast response is suggested. The suggested systems employ the relatively well-known double-loop configuration. They are unusual in the sense that the two multipliers (phase detectors) are replaced by one divider.

Original language	English
Pages (from-to)	368-369
Number of pages	2
Journal	Proceedings of the IEEE
Volume	74
Issue number	2
DOIs	https://doi.org/10.1109/PROC.1986.13466
State	Published - 1 Jan 1986

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/PROC.1986.13466

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title = "A New Fast-Response Double-Loop Phase-Lock Loop",

abstract = "A new method of constructing phase-lock loop systems with wide capture range and fast response is suggested. The suggested systems employ the relatively well-known double-loop configuration. They are unusual in the sense that the two multipliers (phase detectors) are replaced by one divider.",

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year = "1986",

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AU - Wulich, D.

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N2 - A new method of constructing phase-lock loop systems with wide capture range and fast response is suggested. The suggested systems employ the relatively well-known double-loop configuration. They are unusual in the sense that the two multipliers (phase detectors) are replaced by one divider.

AB - A new method of constructing phase-lock loop systems with wide capture range and fast response is suggested. The suggested systems employ the relatively well-known double-loop configuration. They are unusual in the sense that the two multipliers (phase detectors) are replaced by one divider.

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DO - 10.1109/PROC.1986.13466

M3 - Article

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JO - Proceedings of the IEEE

JF - Proceedings of the IEEE

IS - 2

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A New Fast-Response Double-Loop Phase-Lock Loop

Abstract

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