TY - GEN
T1 - A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing
AU - Hassoun, Michael
AU - Kopp, Denny
AU - Monch, Lars
AU - Kalir, Adar
N1 - Funding Information:
Parts of this research were carried out whilst the first author was visiting the Department of Mathematics and Computer Science of the University of Hagen, Germany, in March 2019. This research was partially supported by the iDev 4.0 project. This project is funded by the ECSEL Joint Undertaking (JU) under grant agreement No 783163. The second and fourth author gratefully acknowledge this financial support.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/12/1
Y1 - 2019/12/1
N2 - As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.
AB - As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.
UR - http://www.scopus.com/inward/record.url?scp=85081127151&partnerID=8YFLogxK
U2 - 10.1109/WSC40007.2019.9004654
DO - 10.1109/WSC40007.2019.9004654
M3 - Conference contribution
AN - SCOPUS:85081127151
T3 - Proceedings - Winter Simulation Conference
SP - 2419
EP - 2428
BT - 2019 Winter Simulation Conference, WSC 2019
PB - Institute of Electrical and Electronics Engineers
T2 - 2019 Winter Simulation Conference, WSC 2019
Y2 - 8 December 2019 through 11 December 2019
ER -