A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing

Michael Hassoun; Denny Kopp; Lars Monch; Adar Kalir

doi:10.1109/WSC40007.2019.9004654

A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing

Michael Hassoun, Denny Kopp, Lars Monch, Adar Kalir

Department of Industrial Engineering and Management

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.

Original language	English
Title of host publication	2019 Winter Simulation Conference, WSC 2019
Publisher	Institute of Electrical and Electronics Engineers
Pages	2419-2428
Number of pages	10
ISBN (Electronic)	9781728132839
DOIs	https://doi.org/10.1109/WSC40007.2019.9004654
State	Published - 1 Dec 2019
Event	2019 Winter Simulation Conference, WSC 2019 - National Harbor, United States Duration: 8 Dec 2019 → 11 Dec 2019

Publication series

Name	Proceedings - Winter Simulation Conference
Volume	2019-December
ISSN (Print)	0891-7736

Conference

Conference	2019 Winter Simulation Conference, WSC 2019
Country/Territory	United States
City	National Harbor
Period	8/12/19 → 11/12/19

ASJC Scopus subject areas

Software
Modeling and Simulation
Computer Science Applications

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10.1109/WSC40007.2019.9004654

Cite this

Hassoun, M., Kopp, D., Monch, L., & Kalir, A. (2019). A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing. In 2019 Winter Simulation Conference, WSC 2019 (pp. 2419-2428). Article 9004654 (Proceedings - Winter Simulation Conference; Vol. 2019-December). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/WSC40007.2019.9004654

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title = "A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing",

abstract = "As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.",

author = "Michael Hassoun and Denny Kopp and Lars Monch and Adar Kalir",

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doi = "10.1109/WSC40007.2019.9004654",

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Hassoun, M, Kopp, D, Monch, L & Kalir, A 2019, A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing. in 2019 Winter Simulation Conference, WSC 2019., 9004654, Proceedings - Winter Simulation Conference, vol. 2019-December, Institute of Electrical and Electronics Engineers, pp. 2419-2428, 2019 Winter Simulation Conference, WSC 2019, National Harbor, United States, 8/12/19. https://doi.org/10.1109/WSC40007.2019.9004654

A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing. / Hassoun, Michael; Kopp, Denny; Monch, Lars et al.
2019 Winter Simulation Conference, WSC 2019. Institute of Electrical and Electronics Engineers, 2019. p. 2419-2428 9004654 (Proceedings - Winter Simulation Conference; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.

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A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing

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