As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.