A Novel CDR-Based Low-Cost Time-Interleaved-ADC Timing Calibration

Hananel Faig, David Rohlin, Shai Cohen, Liron Gantz, Nir Sheffi, Dan Sadot

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Digital signal processing (DSP)-based system is a common architecture for high-speed communication links. One of the most important components for DSP-based architectures is the analog-to-digital convertor (ADC). Most of the high-speed ADCs are implemented as time interleaved ADC (TI-ADC). One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The calibration of this mismatch increases system cost and complexity. In this article we propose a new background calibration method based on existing clock and data recovery (CDR) circuits. The timing mismatch can be calibrated using a simple and unique CDR per sub-ADC. Using the existing phase error detector and pulse gain estimator of the regular CDR, the calibration circuit becomes very low-cost, requiring only a first order loop, and a slow numerically controlled oscillator (NCO). VCSEL-based lab experiments are performed, which demonstrate the proposed method efficiency, performance and robustness.

Original languageEnglish
Article number9004541
Pages (from-to)1777-1784
Number of pages8
JournalJournal of Lightwave Technology
Issue number7
StatePublished - 1 Apr 2020


  • CDR
  • TI-ADC
  • Timing calibration
  • digital SerDes
  • optical communication system

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics


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