A scalable architecture for high-speed digital companding

Companding is a well-known signal processing technique exploited by a broad range of applications. It primarily offers reduction of the signal dynamic range while retaining its important attributes. Digital companders have been utilized by a variety of applications, such as voice and video coding, in which the non-linear compression/expansion is typically implemented in software. This paper proposes an efficient parallel architecture for implementing digital compander functionality at very high-speeds. A piecewise linear partitioning of the compression function is applied, driven by prescribed maximal error constraints. The scalability of the scheme in terms of speed and area is discussed. Moreover, it is shown that the architecture can be easily pipelined, yielding further speed enhancement. It is shown that using Xilinx Virtex-II Pro (XC2VP20) FPGA devices, a 20-bit to 8-bit compander is implemented using less than 1000 gates, while operating at over 200 MHz.