A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

Robert Giterman, Adam Teman, Lior Atias, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Embedded memories often constitute over 50% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).

Original languageEnglish
Title of host publication2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509002597
DOIs
StatePublished - 20 Nov 2015
Externally publishedYes
EventIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States
Duration: 5 Oct 20158 Oct 2015

Publication series

Name2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conference

ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/TerritoryUnited States
CityRohnert Park
Period5/10/158/10/15

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