@inproceedings{2c4391a1518d4e69ba976896dab68c98,
title = "A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization",
abstract = " A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm 2 .",
keywords = "CMOS integrated circuits, delay-lines, phase locked loops, phase noise, phased-arrays, radio frequency, tracking loops",
author = "Matan Gal-Katziri and Ali Hajimiri",
note = "Funding Information: This work was sponsored by Caltech{\textquoteright}s Space Solar Power Project (SSPP). Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",
year = "2018",
month = dec,
day = "14",
doi = "10.1109/ASSCC.2018.8579340",
language = "English",
series = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "231--234",
booktitle = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
address = "United States",
}