A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization

Matan Gal-Katziri, Ali Hajimiri

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm 2 .

Original languageEnglish
Title of host publication2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers
Pages231-234
Number of pages4
ISBN (Electronic)9781538664124
DOIs
StatePublished - 14 Dec 2018
Externally publishedYes
Event2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China
Duration: 5 Nov 20187 Nov 2018

Publication series

Name2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/TerritoryTaiwan, Province of China
CityTainan
Period5/11/187/11/18

Keywords

  • CMOS integrated circuits
  • delay-lines
  • phase locked loops
  • phase noise
  • phased-arrays
  • radio frequency
  • tracking loops

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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