Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 104 times higher than the access time. Monte Carlos simulations show that the 2 kb gain-cell array, implemented in a mature 0.18μm CMOS node and supplied with a sub-VT voltage of 400mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.