A transient noise analysis of secured dual-rail based logic style

Kashif Nawaz; Itamar Levi; Francois Xavier Standaert; Denis Flandre

doi:10.1109/NGCAS.2018.8572199

A transient noise analysis of secured dual-rail based logic style

Kashif Nawaz
, Itamar Levi
, Francois Xavier Standaert
, Denis Flandre

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V _DD , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.

Original language	English
Title of host publication	2018 New Generation of CAS, NGCAS 2018
Publisher	Institute of Electrical and Electronics Engineers
Pages	146-149
Number of pages	4
ISBN (Electronic)	9781538676813
DOIs	https://doi.org/10.1109/NGCAS.2018.8572199
State	Published - 10 Dec 2018
Externally published	Yes
Event	2018 New Generation of CAS, NGCAS 2018 - Valletta, Malta Duration: 20 Nov 2018 → 23 Nov 2018

Publication series

Name	2018 New Generation of CAS, NGCAS 2018

Conference

Conference	2018 New Generation of CAS, NGCAS 2018
Country/Territory	Malta
City	Valletta
Period	20/11/18 → 23/11/18

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Energy Engineering and Power Technology
Instrumentation

Access to Document

10.1109/NGCAS.2018.8572199

Cite this

@inproceedings{5b0cf6a50f754f74a3e4e3b51b4b5952,

title = "A transient noise analysis of secured dual-rail based logic style",

abstract = " Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V DD , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.",

author = "Kashif Nawaz and Itamar Levi and Standaert, \{Francois Xavier\} and Denis Flandre",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 New Generation of CAS, NGCAS 2018 ; Conference date: 20-11-2018 Through 23-11-2018",

year = "2018",

month = dec,

day = "10",

doi = "10.1109/NGCAS.2018.8572199",

language = "English",

series = "2018 New Generation of CAS, NGCAS 2018",

publisher = "Institute of Electrical and Electronics Engineers",

pages = "146--149",

booktitle = "2018 New Generation of CAS, NGCAS 2018",

address = "United States",

}

Nawaz, K, Levi, I, Standaert, FX & Flandre, D 2018, A transient noise analysis of secured dual-rail based logic style. in 2018 New Generation of CAS, NGCAS 2018., 8572199, 2018 New Generation of CAS, NGCAS 2018, Institute of Electrical and Electronics Engineers, pp. 146-149, 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, 20/11/18. https://doi.org/10.1109/NGCAS.2018.8572199

A transient noise analysis of secured dual-rail based logic style. / Nawaz, Kashif; Levi, Itamar; Standaert, Francois Xavier et al.
2018 New Generation of CAS, NGCAS 2018. Institute of Electrical and Electronics Engineers, 2018. p. 146-149 8572199 (2018 New Generation of CAS, NGCAS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A transient noise analysis of secured dual-rail based logic style

AU - Nawaz, Kashif

AU - Levi, Itamar

AU - Standaert, Francois Xavier

AU - Flandre, Denis

PY - 2018/12/10

Y1 - 2018/12/10

N2 - Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V DD , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.

AB - Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V DD , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.

UR - https://www.scopus.com/pages/publications/85060198775

U2 - 10.1109/NGCAS.2018.8572199

DO - 10.1109/NGCAS.2018.8572199

M3 - Conference contribution

AN - SCOPUS:85060198775

T3 - 2018 New Generation of CAS, NGCAS 2018

SP - 146

EP - 149

BT - 2018 New Generation of CAS, NGCAS 2018

PB - Institute of Electrical and Electronics Engineers

T2 - 2018 New Generation of CAS, NGCAS 2018

Y2 - 20 November 2018 through 23 November 2018

ER -

A transient noise analysis of secured dual-rail based logic style

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this