abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory

Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this chapter, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.

Original languageEnglish
Title of host publicationVLSI-SoC
Subtitle of host publicationDesign Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Revised and Extended Selected Papers
EditorsAndrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
PublisherSpringer Science and Business Media Deutschland GmbH
Pages343-361
Number of pages19
ISBN (Print)9783030816407
DOIs
StatePublished - 1 Jan 2021
Externally publishedYes
Event28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020 - Virtual, Online
Duration: 6 Oct 20209 Oct 2020

Publication series

NameIFIP Advances in Information and Communication Technology
Volume621
ISSN (Print)1868-4238
ISSN (Electronic)1868-422X

Conference

Conference28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020
CityVirtual, Online
Period6/10/209/10/20

Keywords

  • ISA
  • Memristor
  • RRAM
  • processing-in-memory
  • stateful logic

ASJC Scopus subject areas

  • Information Systems
  • Computer Networks and Communications
  • Information Systems and Management

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