TY - GEN
T1 - AbstractPIM
T2 - 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020
AU - Eliahu, Adi
AU - Ben-Hur, Rotem
AU - Ronen, Ronny
AU - Kvatinsky, Shahar
N1 - Funding Information:
The flexibility and code size reduction advantages of ab-stractPIM come with a cost. The additional execution cycles per benchmark result in proportional additional energy consumption and lower effective lifetime. We believe that higher abstraction is worth the cost of these limitations. VII. CONCLUSIONS This paper presents a hierarchical compilation concept and method for logic execution within a memristive crossbar array. The proposed method provides flexibility, portability, abstraction and code size reduction. The abstractPIM flow lays a solid foundation for a compiler for a memristor-based architecture, by enabling automatic mapping and execution of any logic function within the memory, using a defined ISA. ACKNOWLEDGMENT This research is supported by the ERC under the European Unions Horizon 2020 Research and Innovation Programme (grant agreement no. 757259). REFERENCES
Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/5
Y1 - 2020/10/5
N2 - The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this paper, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.
AB - The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this paper, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.
KW - ISA
KW - Memristor
KW - RRAM
KW - processing-in-memory
KW - stateful logic
UR - http://www.scopus.com/inward/record.url?scp=85101152302&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SOC46417.2020.9344103
DO - 10.1109/VLSI-SOC46417.2020.9344103
M3 - Conference contribution
AN - SCOPUS:85101152302
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 28
EP - 33
BT - 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration, VLSI-SOC 2020
PB - Institute of Electrical and Electronics Engineers
Y2 - 5 October 2020 through 7 October 2020
ER -