Adaptive clock gating for shift register based circuits

Shmuel Wimer, Israel Koren, Itamar Cohen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Clock gating is a widely used technique for dynamic power reduction in VLSI design. In its most straightforward application it allows disabling the clock signal of a flip-flop once its state is no longer subject to changes. This paper extends this technique one step further and proposes a systematic way to achieve additional dynamic power savings based on the correlation of flip-flops' activities. Circuits based on shift registers are widely used in digital systems and we selected them to demonstrate the effectiveness of the proposed method. The best, worst and average cases for dynamic power savings tare analyzed.

Original languageEnglish
Title of host publication2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Pages374-378
Number of pages5
DOIs
StatePublished - 1 Dec 2010
Externally publishedYes
Event2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010 - Eilat, Israel
Duration: 17 Nov 201020 Nov 2010

Publication series

Name2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010

Conference

Conference2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Country/TerritoryIsrael
CityEilat
Period17/11/1020/11/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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