Adaptive multiple-resolution CMOS active pixel sensor

Evgeny Artyomov; Orly Yadid-Pecht

doi:10.1109/TCSI.2006.883161

Adaptive multiple-resolution CMOS active pixel sensor

Evgeny Artyomov, Orly Yadid-Pecht

Unit of Photonics and Electro-Optics Engineering

Research output: Contribution to journal › Article › peer-review

23 Scopus citations

Abstract

A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant and homogeneous backgrounds. The algorithm is implemented on chip in a mixed-signal column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32 × 32 pixels is 70 mW at VDD = 3.3 V.

Original language	English
Pages (from-to)	2178-2186
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	53
Issue number	10
DOIs	https://doi.org/10.1109/TCSI.2006.883161
State	Published - 1 Jan 2006

Keywords

Active pixel sensor (APS)
CMOS imagers
Compression
Image sensor
Multiple resolution
Quadtree decomposition (QTD)
VLSI

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSI.2006.883161

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title = "Adaptive multiple-resolution CMOS active pixel sensor",

abstract = "A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant and homogeneous backgrounds. The algorithm is implemented on chip in a mixed-signal column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32 × 32 pixels is 70 mW at VDD = 3.3 V.",

keywords = "Active pixel sensor (APS), CMOS imagers, Compression, Image sensor, Multiple resolution, Quadtree decomposition (QTD), VLSI",

author = "Evgeny Artyomov and Orly Yadid-Pecht",

note = "Funding Information: Manuscript received December 17, 2003; revised June 14, 2004, and July 3, 2005. This work was supported by the Ministry of Science and performed in the Israeli National CMOS Research Center, Ben-Gurion University, Beer-Shava, Israel. This paper was recommended by Associate Editor T. Arslan.",

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month = jan,

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doi = "10.1109/TCSI.2006.883161",

language = "English",

volume = "53",

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AU - Yadid-Pecht, Orly

N1 - Funding Information: Manuscript received December 17, 2003; revised June 14, 2004, and July 3, 2005. This work was supported by the Ministry of Science and performed in the Israeli National CMOS Research Center, Ben-Gurion University, Beer-Shava, Israel. This paper was recommended by Associate Editor T. Arslan.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant and homogeneous backgrounds. The algorithm is implemented on chip in a mixed-signal column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32 × 32 pixels is 70 mW at VDD = 3.3 V.

AB - A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant and homogeneous backgrounds. The algorithm is implemented on chip in a mixed-signal column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32 × 32 pixels is 70 mW at VDD = 3.3 V.

KW - Active pixel sensor (APS)

KW - CMOS imagers

KW - Compression

KW - Image sensor

KW - Multiple resolution

KW - Quadtree decomposition (QTD)

KW - VLSI

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JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

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Adaptive multiple-resolution CMOS active pixel sensor

Abstract

Keywords

ASJC Scopus subject areas

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