Adaptive multiple resolution CMOS active pixel sensor

Evgeny Artyomov; Orly Yadid-Pecht

Adaptive multiple resolution CMOS active pixel sensor

Evgeny Artyomov, Orly Yadid-Pecht

Department of Electrical & Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS, Typical power dissipation for the test chip with 32×32 pixels is 70mW at VDD = 3.3V.

Original language	English
Pages (from-to)	IV-836-IV-839
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 7 Sep 2004
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Adaptive multiple resolution CMOS active pixel sensor",

abstract = "A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS, Typical power dissipation for the test chip with 32×32 pixels is 70mW at VDD = 3.3V.",

author = "Evgeny Artyomov and Orly Yadid-Pecht",

year = "2004",

month = sep,

day = "7",

language = "English",

volume = "4",

pages = "IV--836--IV--839",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers",

note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

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TY - JOUR

T1 - Adaptive multiple resolution CMOS active pixel sensor

AU - Artyomov, Evgeny

AU - Yadid-Pecht, Orly

PY - 2004/9/7

Y1 - 2004/9/7

N2 - A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS, Typical power dissipation for the test chip with 32×32 pixels is 70mW at VDD = 3.3V.

AB - A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS, Typical power dissipation for the test chip with 32×32 pixels is 70mW at VDD = 3.3V.

UR - http://www.scopus.com/inward/record.url?scp=4344662622&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:4344662622

SN - 0271-4310

VL - 4

SP - IV-836-IV-839

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

Adaptive multiple resolution CMOS active pixel sensor

Abstract

ASJC Scopus subject areas

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