A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35μm 4M2P n-well TSMC CMOS technology available through MOSIS, Typical power dissipation for the test chip with 32×32 pixels is 70mW at VDD = 3.3V.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 7 Sep 2004|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 23 May 2004 → 26 May 2004