All-Digital Integrated Variable-Frequency Variable-Duty-Cycle Modulator with Single-Element Resolution and Single-Cycle Convergence

Research output: Contribution to journalArticlepeer-review

Abstract

This article introduces a new architecture for an all-digital high-resolution (HR) variable-frequency variable-duty-cycle modulator for low-power and area-sensitive applications. Constructed through digital standard-cell delay-line (DL) and simple combinatorial logic, the modulator produces pulse width modulated signals with time-resolution of a single delay-element (DE) for both modulation parameters, thus making it a promising candidate for integration in hybrid controllers of high-frequency switched mode power supplies (SMPSs). Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described in hardware description language (HDL) which translates onto hardware using an automated process. The modulator has been designed on a 0.18- $\mu \text{m}$ 5-V CMOS process, totaling 0.18 mm2 of silicon area as well as on an Altera V field programmable gate array (FPGA) to demonstrate the versatility of the architecture. Experimental results of the FPGA prototype are provided as well as post-layout simulations of the ASIC realization for a variety of mitigation sequences demonstrating single-cycle convergence and time-resolution of 220 and 200 ps, respectively, with excellent linearity characteristics.

Original languageEnglish
Pages (from-to)4270-4283
Number of pages14
JournalIEEE Journal of Emerging and Selected Topics in Power Electronics
Volume11
Issue number4
DOIs
StatePublished - 1 Aug 2023

Keywords

  • ASIC
  • delay line (DL)
  • frequency hopping
  • frequency modulation
  • high resolution (HR)
  • integrated circuits
  • pulsewidth modulation (PWM)

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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