Alternative Logic Families for Energy-Efficient and High Performance Chip Design

With advances in technology and the expansion of mobile applications, energy consumption, which is one of the fundamental limits in both high performance microprocessors and low to medium performance portable systems. With advances in technology and the expansion of mobile applications, energy consumption, which is one of the fundamental limits of both high performance microprocessors and low to medium performance portable systems, has become a primary focus of attention in VLSI digital design [1–6]. In high performance systems, energy and peak power are the limiting factors on further increases in clock speed and circuit density, due to the difficulties of conveying power to circuits and removing the heat they generate. Moreover, the integration of circuits with different workloads and activity profiles results in the formulation of hot spots and temperature gradients over the die. This can impact the long-term reliability and complicate the verification of the processor [7]. In portable battery operated devices such as cellular phones, bio-medical devices, sensor networks, etc., energy consumption is critical since it determines the lifetime of the battery (for non-rechargeables) or the time between recharges. It is also affects the packaging, cost and weight. Many architectures and techniques have been researched, analyzed and proposed for power reduction and energy minimization of combinational circuits [1, 8, 9]. In general, power reduction can be implemented at different levels of design abstraction: the algorithm, system, architecture, gate, circuit and/or the technology. At the algorithm level, for example, methods for simplifying the logic involved in computation and coding for smaller Hamming distances are being developed [10–13].