An improved instruction cache replacement algorithm

Amir Kleen, Erez Stienberg, Moshe Anschel, Yaniv Sibony, Shlomo Greenberg

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Caches are commonly used in DSP architecture, as an alternative for fast on-chip memory, to improve performance by reducing the average memory access latencies. In this paper we propose a new approach for instruction cache performance enhancement, utilizing a-priori knowledge of the program flow to improve the common used LRU replacement algorithm. To improve replacement decision in set-associative caches, we develop a new profile-based algorithm that predicts which code-block will be reused. The proposed algorithm enables the user to affect the cache performance by combining existing LRU hardware and cache dedicated software commands. Simulation results on Starcore's SC140e DSP platform show 2-5% cycle times improvement over the LRU policy for MPEG4 application. Further significant improvement can be achieved when using memories with longer access latencies.

Original languageEnglish
Title of host publicationSiPS 2005
Subtitle of host publicationIEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
Pages573-578
Number of pages6
DOIs
StatePublished - 1 Dec 2005
EventSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece
Duration: 2 Nov 20054 Nov 2005

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume2005
ISSN (Print)1520-6130

Conference

ConferenceSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
Country/TerritoryGreece
CityAthens
Period2/11/054/11/05

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