An SRAM PUF with 2 independent bits/cell in 65nm

Yizhak Shifman, Avi Miller, Yoav Weizman, Alexander Fish, Joseph Shor

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2 per bit.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
StatePublished - 1 Jan 2019
Externally publishedYes
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 26 May 201929 May 2019

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May
ISSN (Print)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/TerritoryJapan
CitySapporo
Period26/05/1929/05/19

Keywords

  • PUF
  • Physical Unclonable Function
  • SRAM

Fingerprint

Dive into the research topics of 'An SRAM PUF with 2 independent bits/cell in 65nm'. Together they form a unique fingerprint.

Cite this