TY - GEN
T1 - Capacitive-loaded push-pull parallel-resonant converter
AU - Edry, Daniel
AU - Ben-Yaakov, Sam
PY - 1993/1/1
Y1 - 1993/1/1
N2 - Results of a theoretical and experimental investigation of a Capacitive-Loaded Push-Pull Parallel-Resonant DC-DC Converter (CL-PPRC), are presented and discussed. The Push-Pull Parallel-Resonant Converter is driven by a lower than resonance frequency and the secondary voltage is rectified and smoothed by a capacitive filter. The CL-PPRC is shown to operate in the zero voltage switching (ZVS) mode with a Boost like DC transfer ratio which is approximately linear with the period of the switching frequency. Experimental results of a 180 Watt, high output voltage (1.8 KV) prototype where found to be in good agreement with the analytical analysis, models and simulation results presented in the paper. The basic characteristic of ZVS, the fact that the resonant current is passing through the switches only during a fraction of the period, the high voltage transfer ratio and the inherent input/output isolation, make the newly proposed topology a viable design alternative in avionic and aerospace applications.
AB - Results of a theoretical and experimental investigation of a Capacitive-Loaded Push-Pull Parallel-Resonant DC-DC Converter (CL-PPRC), are presented and discussed. The Push-Pull Parallel-Resonant Converter is driven by a lower than resonance frequency and the secondary voltage is rectified and smoothed by a capacitive filter. The CL-PPRC is shown to operate in the zero voltage switching (ZVS) mode with a Boost like DC transfer ratio which is approximately linear with the period of the switching frequency. Experimental results of a 180 Watt, high output voltage (1.8 KV) prototype where found to be in good agreement with the analytical analysis, models and simulation results presented in the paper. The basic characteristic of ZVS, the fact that the resonant current is passing through the switches only during a fraction of the period, the high voltage transfer ratio and the inherent input/output isolation, make the newly proposed topology a viable design alternative in avionic and aerospace applications.
UR - http://www.scopus.com/inward/record.url?scp=0027261575&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027261575
SN - 0780309839
T3 - Conference Procedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 51
EP - 57
BT - Conference Procedings - IEEE Applied Power Electronics Conference and Exposition - APEC
PB - Publ by IEEE
T2 - 8th Annual Applied Power Electronic Conference and Exposition - APEC '93
Y2 - 7 March 1993 through 11 March 1993
ER -