Abstract
A novel 256×256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 MSample/s (MS/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35μm 2P4M process, operated by a 3.3V supply and is expected to dissipate 55mW. The total area of the prototype is 12 mm2, and the core area of ADC is 18% from the total area. System architecture and operation are discussed and simulation results are presented.
Original language | English |
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Pages (from-to) | IV-960-IV-963 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
Volume | 4 |
State | Published - 6 Sep 2004 |
Event | 2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering