CMOS APS imager employing 3.3V 12 bit 6.3 MS/S pipelined ADC

Shy Hamami, Leonid Fleshel, Orly Yadid-Pecht

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations


A novel 256×256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 MSample/s (MS/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35μm 2P4M process, operated by a 3.3V supply and is expected to dissipate 55mW. The total area of the prototype is 12 mm2, and the core area of ADC is 18% from the total area. System architecture and operation are discussed and simulation results are presented.

Original languageEnglish
Pages (from-to)IV-960-IV-963
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 6 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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