CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

Shy Hamami, Leonid Fleshel, Orly Yadid-Pecht

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of -0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm2, and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.

Original languageEnglish
Pages (from-to)119-125
Number of pages7
JournalSensors and Actuators, A: Physical
Issue number1
StatePublished - 30 Mar 2007


  • Active pixel sensor
  • Analog-to-digital conversion
  • CMOS imagers
  • Pipelined ADC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Metals and Alloys
  • Electrical and Electronic Engineering


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