CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

Shy Hamami; Leonid Fleshel; Orly Yadid-Pecht

doi:10.1016/j.sna.2006.06.041

CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

Shy Hamami, Leonid Fleshel, Orly Yadid-Pecht

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of -0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm², and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.

Original language	English
Pages (from-to)	119-125
Number of pages	7
Journal	Sensors and Actuators, A: Physical
Volume	135
Issue number	1
DOIs	https://doi.org/10.1016/j.sna.2006.06.041
State	Published - 30 Mar 2007

Keywords

Active pixel sensor
Analog-to-digital conversion
CMOS imagers
Pipelined ADC

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Instrumentation
Condensed Matter Physics
Surfaces, Coatings and Films
Metals and Alloys
Electrical and Electronic Engineering

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10.1016/j.sna.2006.06.041

Cite this

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title = "CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC",

abstract = "This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of -0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm2, and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.",

keywords = "Active pixel sensor, Analog-to-digital conversion, CMOS imagers, Pipelined ADC",

author = "Shy Hamami and Leonid Fleshel and Orly Yadid-Pecht",

note = "Funding Information: The authors acknowledge the financial support of the Israeli Ministry of Defense and Mr. Shai Diller for helpful assistance and discussions. The fabrication was carried out through MOSIS. ",

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doi = "10.1016/j.sna.2006.06.041",

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T1 - CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

AU - Hamami, Shy

AU - Fleshel, Leonid

AU - Yadid-Pecht, Orly

N1 - Funding Information: The authors acknowledge the financial support of the Israeli Ministry of Defense and Mr. Shai Diller for helpful assistance and discussions. The fabrication was carried out through MOSIS.

PY - 2007/3/30

Y1 - 2007/3/30

N2 - This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of -0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm2, and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.

AB - This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of -0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm2, and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.

KW - Active pixel sensor

KW - Analog-to-digital conversion

KW - CMOS imagers

KW - Pipelined ADC

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JO - Sensors and Actuators, A: Physical

JF - Sensors and Actuators, A: Physical

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CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

Abstract

Keywords

ASJC Scopus subject areas

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