Optical fault injection attacks can be used to induce errors into cryptographic circuits during sensitive calculations in order to reveal the secret information inside the system. In high-end fault injection setup, the adversary may use high resolution laser to inject localized faults. Most of the existing sensors that aim to detect these kind of attacks are big in area and therefore in many cases can be easily detected. In addition, these sensors are custom designed IPs and can't be implemented using standard digital design flow. In this paper we present a very simple and compact (area of 2.3μτη2 in 65nm CMOS technology) digital detector that can be implemented in a distributed manner as part of the digital logic during the design flow, near sensitive locations. The proposed sensor operates in the sub-threshold region and consumes low static power of 366pW (@ VDD = 1.2V). post-Layout simulation results shows that while the sensor is 10X more sensitive than a minimum sized CMOS inverter, it is robust against false alarms.