DC Link Capacitance Reduction in PFC Rectifiers Employing PI+Notch Voltage Controllers

Pavel Strajnikov, Alon Kuperman

Research output: Contribution to journalArticlepeer-review

Abstract

It is well-known that adding a notch filter in series with the typically employed type-II (or PI) regulator allows improving the trade-off between DC link voltage dynamics and grid-side current total harmonic distortion (THD) in practical single-phase power factor correction rectifiers (PFCR). The paper demonstrates that notch filter utilization alternatively allows reducing the value of DC link capacitance in case hold-up time requirement is absent. The revealed value of minimum capacitance is expressed by explicit function of possible mains frequency values range, maximum expected grid voltage magnitude, rated system power, DC link voltage set point, maximum tolerable grid-side current THD and the desired phase margin (PM) of DC link voltage loop. It is demonstrated that the proposed approach yields 4-fold reduction of DC link capacitance for typical values of 5% tolerable grid-side current THD under 40o PM constraint. Experimental results exhibit close-fitting resemblance to corresponding analytical predictions, verifying the proposed methodology.

Original languageEnglish
Pages (from-to)1-9
Number of pages9
JournalIEEE Transactions on Power Electronics
DOIs
StateAccepted/In press - 1 Jan 2022

Keywords

  • Capacitance
  • DC link capacitance
  • Harmonic analysis
  • Notch filters
  • PI+Notch controller
  • Power factor correction
  • Regulators
  • Steady-state
  • THD
  • transient response
  • Voltage
  • Voltage control

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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