Debug port controller architectures for system-on-chip integrated circuits

Dimitry Akselrod; Arie Margulis

doi:10.1109/CCECE.2008.4564813

Debug port controller architectures for system-on-chip integrated circuits

Dimitry Akselrod
, Arie Margulis

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Since its introduction, Test Access Port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuit's functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.

Original language	English
Title of host publication	IEEE Canadian Conference on Electrical and Computer Engineering, Proceedings, CCECE 2008
Pages	1605-1610
Number of pages	6
DOIs	https://doi.org/10.1109/CCECE.2008.4564813
State	Published - 22 Sep 2008
Externally published	Yes
Event	IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2008 - Niagara Falls, ON, Canada Duration: 4 May 2008 → 7 May 2008

Publication series

Name	Canadian Conference on Electrical and Computer Engineering
ISSN (Print)	0840-7789

Conference

Conference	IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2008
Country/Territory	Canada
City	Niagara Falls, ON
Period	4/05/08 → 7/05/08

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/CCECE.2008.4564813

Cite this

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title = "Debug port controller architectures for system-on-chip integrated circuits",

abstract = "Since its introduction, Test Access Port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuit's functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.",

author = "Dimitry Akselrod and Arie Margulis",

year = "2008",

month = sep,

day = "22",

doi = "10.1109/CCECE.2008.4564813",

language = "English",

isbn = "9781424416431",

series = "Canadian Conference on Electrical and Computer Engineering",

pages = "1605--1610",

booktitle = "IEEE Canadian Conference on Electrical and Computer Engineering, Proceedings, CCECE 2008",

note = "IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2008 ; Conference date: 04-05-2008 Through 07-05-2008",

}

Akselrod, D & Margulis, A 2008, Debug port controller architectures for system-on-chip integrated circuits. in IEEE Canadian Conference on Electrical and Computer Engineering, Proceedings, CCECE 2008., 4564813, Canadian Conference on Electrical and Computer Engineering, pp. 1605-1610, IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2008, Niagara Falls, ON, Canada, 4/05/08. https://doi.org/10.1109/CCECE.2008.4564813

Debug port controller architectures for system-on-chip integrated circuits. / Akselrod, Dimitry; Margulis, Arie.
IEEE Canadian Conference on Electrical and Computer Engineering, Proceedings, CCECE 2008. 2008. p. 1605-1610 4564813 (Canadian Conference on Electrical and Computer Engineering).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Since its introduction, Test Access Port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuit's functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.

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ER -

Debug port controller architectures for system-on-chip integrated circuits

Abstract

Publication series

Conference

UN SDGs

ASJC Scopus subject areas

Access to Document

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Cite this