A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.