Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications

Arthur Spivak; Orly Yadid-Pecht

doi:10.1109/ISCAS.2014.6865061

Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications

Arthur Spivak, Orly Yadid-Pecht

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers
Pages	45-48
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865061
State	Published - 1 Jan 2014
Externally published	Yes
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 1 Jun 2014 → 5 Jun 2014

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	1/06/14 → 5/06/14

Keywords

Active Pixel Sensor (APS)
CMOS Image Sensors
Charge Transfer
Low Light
Low Noise
Sensor

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865061

Cite this

Spivak, A., & Yadid-Pecht, O. (2014). Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 45-48). Article 6865061 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2014.6865061

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abstract = "A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.",

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Spivak, A & Yadid-Pecht, O 2014, Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865061, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers, pp. 45-48, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865061

Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications. / Spivak, Arthur; Yadid-Pecht, Orly.
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers, 2014. p. 45-48 6865061 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.

AB - A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.

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ER -

Spivak A, Yadid-Pecht O. Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers. 2014. p. 45-48. 6865061. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2014.6865061

Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications

Abstract

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Keywords

ASJC Scopus subject areas

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