Design verification of digital systems based on logic programming

It has already been shown how Prolog can be used as a hardware description language. Prolog enables the use of the hierarchical structure of a design by breaking the design into pieces and using the verification strategy recursively. Moreover, Prolog enables a dynamic updating of a database such that the correctness of each type of module is proved exactly once and recorded, so that use can be made of them later in the verification process. Thus, the complexity of the verification process is proportional to the number of different types of modules and not to the number of primitive components. In short, the use of Prolog offers a rare combination of convenient hardware description tools, applications of software techniques in hardware manipulations, and the application of AI concepts. Further major considerations, not treated until now, are presented in this paper. A design verification program named SYMEX, which is based on symbolic execution, is treated in detail, demonstrating how Prolog deals with the following fundamental issues: (a) An inductive proof of a module with N inputs; (b) A natural treatment of input and output sequences having an undefined length; (c) Information transfer in and out of a design; (d) A structural analysis of a module.