Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs

Gilad Katz, Russ Romano, Tony Zortea

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-bit DAC. Simulation results and lab measurements of a TSMC 16 nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.

Original languageEnglish
Pages (from-to)83-88
Number of pages6
JournalAEU - International Journal of Electronics and Communications
Volume107
DOIs
StatePublished - 1 Jul 2019
Externally publishedYes

Keywords

  • Calibration
  • Digital to analog converter (DAC)
  • PAM4
  • Sample-time error (STE)
  • Skew
  • Time-interleaved

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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