Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs

Gilad Katz; Russ Romano; Tony Zortea

doi:10.1016/j.aeue.2019.04.026

Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs

Gilad Katz, Russ Romano, Tony Zortea

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-bit DAC. Simulation results and lab measurements of a TSMC 16 nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.

Original language	English
Pages (from-to)	83-88
Number of pages	6
Journal	AEU - International Journal of Electronics and Communications
Volume	107
DOIs	https://doi.org/10.1016/j.aeue.2019.04.026
State	Published - 1 Jul 2019
Externally published	Yes

Keywords

Calibration
Digital to analog converter (DAC)
PAM4
Sample-time error (STE)
Skew
Time-interleaved

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1016/j.aeue.2019.04.026

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title = "Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs",

abstract = "Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-bit DAC. Simulation results and lab measurements of a TSMC 16 nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.",

keywords = "Calibration, Digital to analog converter (DAC), PAM4, Sample-time error (STE), Skew, Time-interleaved",

author = "Gilad Katz and Russ Romano and Tony Zortea",

note = "Publisher Copyright: {\textcopyright} 2019 Elsevier GmbH",

year = "2019",

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doi = "10.1016/j.aeue.2019.04.026",

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AU - Katz, Gilad

AU - Romano, Russ

AU - Zortea, Tony

PY - 2019/7/1

Y1 - 2019/7/1

N2 - Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-bit DAC. Simulation results and lab measurements of a TSMC 16 nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.

AB - Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-bit DAC. Simulation results and lab measurements of a TSMC 16 nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.

KW - Calibration

KW - Digital to analog converter (DAC)

KW - PAM4

KW - Sample-time error (STE)

KW - Skew

KW - Time-interleaved

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EP - 88

JO - AEU - International Journal of Electronics and Communications

JF - AEU - International Journal of Electronics and Communications

SN - 1434-8411

ER -

Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs

Abstract

Keywords

ASJC Scopus subject areas

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