TY - GEN
T1 - Digital multiphase PWM integrated module generated from a single synchronization source
AU - Urkin, Tom
AU - Peretz, Mor Mordechai
N1 - Funding Information:
This research was supported by the ISRAEL SCIENCE FOUNDATION grant number 2186/19. This research was supported by Vishay Ltd., Siliconix division.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/6/14
Y1 - 2021/6/14
N2 - This paper introduces a new architecture for a high-resolution digital pulse-width modulator (HR-DPWM) which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay-element. To minimize the statistical error spread (e.g. jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18μm 5V CMOS process, totaling 0.08mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200ps and excellent matching and tracking between all phases.
AB - This paper introduces a new architecture for a high-resolution digital pulse-width modulator (HR-DPWM) which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay-element. To minimize the statistical error spread (e.g. jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18μm 5V CMOS process, totaling 0.08mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200ps and excellent matching and tracking between all phases.
KW - Delay-line
KW - Digital control
KW - Digital pulse-width modulator
KW - Multiphase converter
UR - http://www.scopus.com/inward/record.url?scp=85115717900&partnerID=8YFLogxK
U2 - 10.1109/APEC42165.2021.9487374
DO - 10.1109/APEC42165.2021.9487374
M3 - Conference contribution
AN - SCOPUS:85115717900
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1001
EP - 1007
BT - 2021 IEEE Applied Power Electronics Conference and Exposition, APEC 2021
PB - Institute of Electrical and Electronics Engineers
T2 - 36th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2021
Y2 - 14 June 2021 through 17 June 2021
ER -