TY - JOUR
T1 - Digital Multiphase PWM Integrated Module Generated from a Single Synchronization Source
AU - Urkin, Tom
AU - Kuperman, Alon
AU - Peretz, Mor Mordechai
N1 - Funding Information:
This work was supported in part by the Israel Science Foundation under Grant 2186/19 and in part by the Vishay Ltd., Siliconix IC division.
Publisher Copyright:
© 1986-2012 IEEE.
PY - 2022/2/1
Y1 - 2022/2/1
N2 - This article introduces a new architecture for a high-resolution digital pulsewidth modulator (HR-DPWM), which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay element. To minimize the statistical error spread (e.g., jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty-ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18 μm 5 V CMOS process, totaling 0.08 mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200 ps and excellent matching and tracking between all phases.
AB - This article introduces a new architecture for a high-resolution digital pulsewidth modulator (HR-DPWM), which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay element. To minimize the statistical error spread (e.g., jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty-ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18 μm 5 V CMOS process, totaling 0.08 mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200 ps and excellent matching and tracking between all phases.
KW - Delay-line
KW - digital control
KW - digital pulsewidth modulator
KW - multiphase converter
UR - http://www.scopus.com/inward/record.url?scp=85117408371&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2021.3107420
DO - 10.1109/TPEL.2021.3107420
M3 - Article
AN - SCOPUS:85117408371
SN - 0885-8993
VL - 37
SP - 1570
EP - 1578
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 2
ER -