Dual VDD block based CMOS image sensor - Preliminary evaluation

Qing Gao; Orly Yadid-Pecht

doi:10.1109/ISCAS.2011.5937939

Dual VDD block based CMOS image sensor - Preliminary evaluation

Qing Gao, Orly Yadid-Pecht

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

An image sensor with dual power supply of 1.8V and 1.1V is proposed. The sensor works on blocks of 88 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, 1.8V is chosen to achieve high imaging performance; otherwise, 1.1V is used to save power. Preliminary evaluation of the imager performance based on simulations for TSMC 0.18 m CMOS technology is given. The estimated amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB).

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	1820-1823
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937939
State	Published - 2 Aug 2011
Externally published	Yes
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2011.5937939

Cite this

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title = "Dual VDD block based CMOS image sensor - Preliminary evaluation",

abstract = "An image sensor with dual power supply of 1.8V and 1.1V is proposed. The sensor works on blocks of 88 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, 1.8V is chosen to achieve high imaging performance; otherwise, 1.1V is used to save power. Preliminary evaluation of the imager performance based on simulations for TSMC 0.18 m CMOS technology is given. The estimated amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB).",

author = "Qing Gao and Orly Yadid-Pecht",

year = "2011",

month = aug,

day = "2",

doi = "10.1109/ISCAS.2011.5937939",

language = "English",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1820--1823",

booktitle = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011",

note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

Gao, Q & Yadid-Pecht, O 2011, Dual VDD block based CMOS image sensor - Preliminary evaluation. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937939, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1820-1823, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937939

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AU - Yadid-Pecht, Orly

PY - 2011/8/2

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N2 - An image sensor with dual power supply of 1.8V and 1.1V is proposed. The sensor works on blocks of 88 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, 1.8V is chosen to achieve high imaging performance; otherwise, 1.1V is used to save power. Preliminary evaluation of the imager performance based on simulations for TSMC 0.18 m CMOS technology is given. The estimated amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB).

AB - An image sensor with dual power supply of 1.8V and 1.1V is proposed. The sensor works on blocks of 88 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, 1.8V is chosen to achieve high imaging performance; otherwise, 1.1V is used to save power. Preliminary evaluation of the imager performance based on simulations for TSMC 0.18 m CMOS technology is given. The estimated amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB).

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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ER -

Dual VDD block based CMOS image sensor - Preliminary evaluation

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