Efficiency of Dual Mode Logic in Nanoscale Technology Nodes

Netanel Shavit; Ramiro Taco; Alexander Fish

doi:10.1109/ICSEE.2018.8646267

Efficiency of Dual Mode Logic in Nanoscale Technology Nodes

Netanel Shavit, Ramiro Taco, Alexander Fish

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The impact of intrinsic capacitance, logic depth and robustness are analyzed for a wide power supply range. For this purpose, two benchmarks were implemented and compared to CMOS. Results show up to 22% better performance in terms of speed and up to 24% in terms of energy when the circuit operates in the dynamic and static mode, respectively.

Original language	English
Title of host publication	2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018
Publisher	Institute of Electrical and Electronics Engineers
ISBN (Electronic)	9781538663783
DOIs	https://doi.org/10.1109/ICSEE.2018.8646267
State	Published - 2 Jul 2018
Externally published	Yes
Event	2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018 - Eilat, Israel Duration: 12 Dec 2018 → 14 Dec 2018

Publication series

Name	2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018

Conference

Conference	2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018
Country/Territory	Israel
City	Eilat
Period	12/12/18 → 14/12/18

Keywords

CMOS
alternative logic family
dual mode logic (DML)
nanoscaled technology nodes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICSEE.2018.8646267

Cite this

Shavit, N., Taco, R., & Fish, A. (2018). Efficiency of Dual Mode Logic in Nanoscale Technology Nodes. In 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018 Article 8646267 (2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICSEE.2018.8646267

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title = "Efficiency of Dual Mode Logic in Nanoscale Technology Nodes",

abstract = "Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The impact of intrinsic capacitance, logic depth and robustness are analyzed for a wide power supply range. For this purpose, two benchmarks were implemented and compared to CMOS. Results show up to 22% better performance in terms of speed and up to 24% in terms of energy when the circuit operates in the dynamic and static mode, respectively.",

keywords = "CMOS, alternative logic family, dual mode logic (DML), nanoscaled technology nodes",

author = "Netanel Shavit and Ramiro Taco and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018 ; Conference date: 12-12-2018 Through 14-12-2018",

year = "2018",

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doi = "10.1109/ICSEE.2018.8646267",

language = "English",

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Shavit, N, Taco, R & Fish, A 2018, Efficiency of Dual Mode Logic in Nanoscale Technology Nodes. in 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018., 8646267, 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018, Institute of Electrical and Electronics Engineers, 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018, Eilat, Israel, 12/12/18. https://doi.org/10.1109/ICSEE.2018.8646267

Efficiency of Dual Mode Logic in Nanoscale Technology Nodes. / Shavit, Netanel; Taco, Ramiro; Fish, Alexander.
2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018. Institute of Electrical and Electronics Engineers, 2018. 8646267 (2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2018/7/2

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N2 - Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The impact of intrinsic capacitance, logic depth and robustness are analyzed for a wide power supply range. For this purpose, two benchmarks were implemented and compared to CMOS. Results show up to 22% better performance in terms of speed and up to 24% in terms of energy when the circuit operates in the dynamic and static mode, respectively.

AB - Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The impact of intrinsic capacitance, logic depth and robustness are analyzed for a wide power supply range. For this purpose, two benchmarks were implemented and compared to CMOS. Results show up to 22% better performance in terms of speed and up to 24% in terms of energy when the circuit operates in the dynamic and static mode, respectively.

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Shavit N, Taco R, Fish A. Efficiency of Dual Mode Logic in Nanoscale Technology Nodes. In 2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018. Institute of Electrical and Electronics Engineers. 2018. 8646267. (2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018). doi: 10.1109/ICSEE.2018.8646267

Efficiency of Dual Mode Logic in Nanoscale Technology Nodes

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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