Efficiency of Dual Mode Logic in Nanoscale Technology Nodes

Netanel Shavit, Ramiro Taco, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The impact of intrinsic capacitance, logic depth and robustness are analyzed for a wide power supply range. For this purpose, two benchmarks were implemented and compared to CMOS. Results show up to 22% better performance in terms of speed and up to 24% in terms of energy when the circuit operates in the dynamic and static mode, respectively.

Original languageEnglish
Title of host publication2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538663783
DOIs
StatePublished - 20 Feb 2019
Externally publishedYes
Event2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018 - Eilat, Israel
Duration: 12 Dec 201814 Dec 2018

Publication series

Name2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018

Conference

Conference2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018
Country/TerritoryIsrael
CityEilat
Period12/12/1814/12/18

Keywords

  • CMOS
  • alternative logic family
  • dual mode logic (DML)
  • nanoscaled technology nodes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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