Abstract
In this brief, an efficient voltage scalable switched capacitor converter (SCC) for 1.1 V battery-powered digital system is presented. The SCC employs a binary resolution technique to preserve high efficiency at load voltages down to sub-200 mV while keeping the efficiency high. The proposed converter can be configured into four topologies to support subthreshold output levels of 0.18-0.6 V. The converter is designed in a standard lowpower 40-nm CMOS TSMC process. Simulation results show that the efficiency of the SCC can be improved by 10%-11% in the vicinity of VDD=200mV as compared to one using a conventional approach. An optimization strategy for designing multi-topology SCC is presented to improve the effectiveness of the circuit and to preserve efficiency over large load voltages.
Original language | English |
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Article number | 6423300 |
Pages (from-to) | 2353-2357 |
Number of pages | 5 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 21 |
Issue number | 12 |
DOIs | |
State | Published - 1 Feb 2013 |
Keywords
- Dc-dc power converter
- design optimization
- low-power electronics
- subthreshold design
- switched capacitor circuits
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering