Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline

Research output: Contribution to journalArticlepeer-review


Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoiding CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based multithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

Original languageEnglish
Pages (from-to)735-745
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number2
StatePublished - 1 Feb 2022


  • Computer architecture
  • Decoding
  • Hardware
  • Instruction sets
  • Multithreading
  • Pipelines
  • Registers

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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