Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. A common ADC architecture is based on sample-and-hold (S/H) circuits, where the acquired signal is observed in repeated intervals of fixed duration, referred to as the sampling time, and is not utilized for the entire duration. In this paper, we extend the structure of S/H ADCs, allowing them to harvest energy from the observed signal by modifying the circuitry during hold time of the sampling process of an ADC. This harvested energy can be used to supplement the ADC itself, paving the way to the possibility of zero power and power saving ADCs. We analyze the tradeoff between the ability to accurately recover the sampled signal and the energy harvesting which arises from the proposed ADC architecture, and provide guidelines to setting the sampling rate in light of accuracy and energy constraints. Our numerical evaluations indicate that energy harvesting ADCs operating with up to 16 bits per sample can acquire analog signals such that they can be recovered with minimal errors without requiring power from the external source.