eSampling: Energy harvesting ADCs

The power consumption of analog-to-digital converters (ADCs) imposes a major challenge in power-limited systems. A common ADC architecture is based on sample-and-hold (S/H) circuits, where the analog signal is tracked only for a fraction of the sampling period. In this paper, we propose eSampling ADCs, which extend the structure of S/H ADCs without altering the conversion procedure, while allowing energy harvesting from the analog signal during the time periods where the signal is not tracked. The amount of energy harvested can be increased by reducing the sampling rate. We analyze the tradeoff between signal recovery and the energy harvested, and provide guidelines for setting the sampling rate in light of accuracy and energy constraints. Further, the feasibility of eSampling ADCs is validated by simulating a circuit-level design of an 8-bit eSampling ADC in standard CMOS 65 nm technology. The implemented ADC operates at a supply voltage of 1V and sampling rate of 40 MHz. Our analysis shows that eSampling ADCs are able to perfectly recover (up to the distortion induced by quantization) the acquired bandlimited analog signals, while harvesting a significant fraction of the power consumed in acquisition. The experiment demonstrates that eSampling ADC can harvest 21.5% of the energy it spends during analog-to-digital conversion, without affecting the accuracy in reconstructing the analog signal. Finally, we establish the effectiveness of the proposed system by powering a commonly used on-system circuitry operational amplifier (op-amp) entirely using the harvested energy.