TY - GEN
T1 - Evaluation of Dual Mode Logic in 28nm FD-SOI technology
AU - Taco, Ramiro
AU - Levi, Itamar
AU - Lanuzza, Marco
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technology, with the goal of improving energy efficiency for wide supply voltage operation range. By combining the operating characteristics of the DML and the extended body bias capability of the technology, energy efficient digital circuits that can effectively benefit from adaptive voltage and frequency scaling techniques can be defined. This manuscript reports evaluations of the DML against conventional static and dynamic CMOS logics for two benchmarks in the 0.3V-1V supply voltage range. First, a NAND-NOR chain was considered. Simulation results showed that the DML approach assures roughly the 40% savings in terms of energy consumption with respect to the static CMOS implementation and improves the speed about 20% in comparison to the dynamic CMOS design. Second, a 16-bit Carry Skip Adder was considered. Due to the unique capability of the DML to switch on-the-fly between static and dynamic modes of operation, an improvement of more than 20% in terms of EDP was obtained in comparison to the conventional CMOS adder design.
AB - For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technology, with the goal of improving energy efficiency for wide supply voltage operation range. By combining the operating characteristics of the DML and the extended body bias capability of the technology, energy efficient digital circuits that can effectively benefit from adaptive voltage and frequency scaling techniques can be defined. This manuscript reports evaluations of the DML against conventional static and dynamic CMOS logics for two benchmarks in the 0.3V-1V supply voltage range. First, a NAND-NOR chain was considered. Simulation results showed that the DML approach assures roughly the 40% savings in terms of energy consumption with respect to the static CMOS implementation and improves the speed about 20% in comparison to the dynamic CMOS design. Second, a 16-bit Carry Skip Adder was considered. Due to the unique capability of the DML to switch on-the-fly between static and dynamic modes of operation, an improvement of more than 20% in terms of EDP was obtained in comparison to the conventional CMOS adder design.
KW - Dual mode logic (DML)
KW - low power
UR - http://www.scopus.com/inward/record.url?scp=85032688284&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050998
DO - 10.1109/ISCAS.2017.8050998
M3 - Conference contribution
AN - SCOPUS:85032688284
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -
