Evolution of graphics northbridge test and debug architectures across four generations of AMD ASICs

The article provides an insight into the evolution of Graphics Northbridge (GNB) DFx architectures across four generations of AMD Application Specific Integrated Circuit (ASIC), including the first AMD fusion accelerated processor unit (APU): Llano. The Llano APU GNB is split into 52 macroblocks or 'tiles.' A tile is a standalone entity from a physical point of view. Synthesis, scan insertion, and static timing analysis are done at this level of hierarchy. Some functional IPs can be divided into a number of tiles, whereas some tiles could contain a number of IPs. The SoC design utilized clocks from on-die PLL for at-speed scan testing. Scan launch and capture control in the GNB was decentralized and used dedicated logic in each tile. The DSM is a general purpose state machine for triggering and tracing of the debug bus. The DSMs are coupled with on-chip tracing allowing saving a history of debug bus activity.