@inproceedings{e681da0b62c84613853724bd07468faf,
title = "Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology",
abstract = "In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (ED) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.",
keywords = "Adaptive energy-efficient digital design, Dual mode logic, FD-SOI",
author = "Ramiro Taco and Leonid Yavits and Netanel Shavit and Inbal Stanger and Marco Lanuzza and Alexander Fish",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",
year = "2020",
month = jan,
day = "1",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers",
booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",
address = "United States",
}
