@inproceedings{4212a805bac142979816c878ea456014,
title = "FPGA-based data compressor based on prediction by partial matching",
abstract = "We design and develop a data compression engine on a single FPGA chip that is used as part of a text-classification application. The implementation of the prediction by partial matching algorithm and arithmetic coding data compression is totally in hardware without any software code. Our design implements a dynamic data structure to store the symbol frequency counts up to maximal order of 2. The computation of the tag-interval that encodes the data sequence in arithmetic coding is done in a parallel architecture that achieves a high speedup factor. Even with a relatively slow 50 Mhz clock our hardware engine performs more than 70 times faster than a software-based implementation in C on a CPU running on a 3 Ghz clock.",
keywords = "Data compression, FPGA, parallel architecture",
author = "Joel Ratsaby and Vadim Sirota",
year = "2012",
month = dec,
day = "1",
doi = "10.1109/EEEI.2012.6377120",
language = "English",
isbn = "9781467346801",
series = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012",
booktitle = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012",
note = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012 ; Conference date: 14-11-2012 Through 17-11-2012",
}